FIGS. 8(a) and 8(b) are diagrams illustrating a prior art compound semiconductor device where FIG. 8(a) is a plan view showing a device structure of GaAs system MESFET and FIG. 8(b) is a cross-sectional view in line E-E' of FIG. 8(a). In the figures, reference numeral 20 designates a GaAs substrate. A GaAs buffer layer 21 is disposed on the GaAs substrate 20. A low concentration n.sup.- type GaAs semiconductor layer 22 serving as a channel layer is produced by ion implantation on the buffer layer 21. High concentration n.sup.+ type GaAs semiconductor layers 23 are produced by ion implantation at source and drain regions at both sides of the channel layer 22. A recess 24 is produced at a prescribed portion of the channel layer 22. A gate electrode 1 is disposed on the recess 24 to provide a Schottky junction. A first ion implantation region 3 as an insulating region for element separation is produced by ion implantation employing H or the like as ion source at the entire contour of the periphery of the device region. Ohmic electrodes 2 of source and drain are produced on the device region and a part of the insulating region. Here, the fat line in FIG. 8(a) shows a boundary of the metal electrodes.
The production method and the function of the device will be described.
An n.sup.- type GaAs semiconductor layer 22 of low impurity concentration of above 1.times.10.sup.17 cm.sup.-3 which serves as a channel layer is produced by impurity implantation on the buffer layer 21 of impurity concentration of below 1.times.10.sup.16 cm.sup.-3 produced on a GaAs semiconductor substrate 20, and at the source and drain production regions sandwiching the gate production region in the n.sup.- type GaAs semiconductor layer 22 which serves as the channel layer, source and drain regions comprising n.sup.+ type GaAs semiconductor layer 23 of high concentration of above 3.times.10.sup.17 cm.sup.-3 are produced by impurity implantation. Thereafter, insulation implantation is carried out into the entire crystal growth layers 21 and 22 containing carriers therein at the periphery of the transistor using photoresist (not shown) as a mask, thereby first ion implantation regions 3 are produced to perform element separation. Thereafter, a source and a drain electrodes 2 are produced on the n.sup.+ type GaAs semiconductor layer 23 at once, and a portion of the n.sup.- type GaAs semiconductor layer 22 is recess etched to produce a recess 24 with adjusting the device characteristics utilizing variation in saturation current between the source and drain electrodes. Thereafter, a gate electrode 1 is produced so as to have a Schottky junction on the recess 24.
The GaAs system MESFET having the above-described structure functions to operate a transistor operation in which the current I.sub.ds between the source and the drain is controlled by the gate voltage applied to the gate electrode 1. In addition, in the GaAs system MESFET, the device isolation is performed by an element separation employing ion implantation.
In the GaAs system MESFET device in which the device isolation is performed by ion implantation as described above, there are problems that variations in the gate junction breakdown voltage, particularly, reductions in the gate breakdown voltage are caused by process variations such as variations in the epitaxial wafer produced dependent on the wafer process and variations in the gate process or the like. In other words, when concentration of electric field occurs, the gate breakdown voltage is dependent on the intensity of the electric field, the way of attachment of the Schottky junction gate electrode, a wafer (bulk) state, and the way of formation of the insulating interface between the insulating layer and the portion of the active layer of the FET, and these vary with the process variations.
When concentration of electric field occurs at a portion of the insulating interface between the insulating layer and the active layer of the FET dependent on these varying factors, there arises an interface leakage of a current. In a case of recess type gate structure, because the etching rate is different between the insulating region and the active layer portion, a step due to the etching is produced at the interface between the insulating region 3 and the active layer portion 2a as shown in FIG. 10, and when this step is fairly steep, it causes breakage of the gate electrode 1 that is produced thereon and destruction of the gate oxide film. As a result, the gate breakdown voltage is reduced so that gate destruction is likely to arise. Because of such reduction in the gate breakdown voltage, reliability of the device is also reduced.